SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

Japanese Patent JP3532788

B2

PROBLEM TO BE SOLVED: To shorten wiring length, and to achieve straight wiring by forming a conductor layer corresponding to connection wiring on the junction surface of one of a plurality of semiconductor substrates, and by mutually connecting the connection wiring being formed on each semiconductor substrate.
SOLUTION: On a pair of semiconductor substrates 1 and 2, where a semiconductor element is mounted, wring layers 3 and 4 that are the wiring of each semiconductor element are formed, and through-holes 5 and 6 used as connection wiring being formed in a hole part are electrically interlocked to the wiring layers 3 and 4. Also, one each of the semiconductor substrates 1 and 2, insulating layers 7 and 8 are each laminate molded, and each of the through-hole wirings 5 and 6 is formed by filling a conductive material into through-holes 14 and 15 provided in the insulating layers 7 and 8. Furthermore, on each of the insulating layers 7 and 8, connection wiring layer 9 and 10 made of a conductive metal or the like is laminate molded.

Suga, Tadatomo

JP10597099A

May 31, 2004

April 13, 1999

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Suga, Tadatomo
SONY CORP
FUJITSU LTD
OKI ELECTRIC IND CO LTD
SANYO ELECTRIC CO LTD
SHARP CORP
TOSHIBA CORP
NEC CORP
HITACHI LTD
MATSUSHITA ELECTRONICS INDUSTRY CORP
MITSUBISHI ELECTRIC CORP
ROHM CO LTD

H01L27/04; H01L21/02; H01L21/3205; H01L21/768; H01L23/52; H01L23/552; H01L23/58; H01L27/00; (IPC1-7): H01L21/768; H01L21/02; H01L21/3205; H01L27/00

伊賀 誠司 （外２名）
小池 晃 （外１名）
小池 晃 （外２名）

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