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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH03185900
Kind Code:
A
Abstract:

PURPOSE: To perform highly integrated packaging and high-efficiency cooling of an ingot simultaneously by a method wherein a wiring metal film is formed on the outer surface of the ingot formed into a polyhedron, a cylindrical body or a spherical body in a prescribed pattern and semiconductor chips, which are connected to the wiring metal film, are mounted on the outer surface of the ingot.

CONSTITUTION: IC chips 2 are adhered on the whole periphery of the outer surface of a hollow and polyhedral silicon ingot 1 at prescribed arrangement intervals. The ingot 1 is arranged its external shape into a hexagonal pillar by a chamfering work, for example, and the outer diameter and height of the hexagonal pillar are respectively set in a dimension to correspond to a mounting density, but the diameter of a hollow part 3 is provided comparatively large for improving a cooling effect. The individual IC chips 2 are directly formed on the ingot 1 in the same method as the manufacturing method of normal semiconductor element. In case the member of the IC chips 2 is high and the IC chips are formed on the whole periphery of the ingot 1, the heat generation at the time of operation of the ingot becomes a considerable one. Then a cooling medium is circulated in the hollow of the ingot 1. Thereby, the cooling of the ingot is performed.


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Inventors:
IMAI TOMIO
KAMATA CHIYOSHI
Application Number:
JP32374589A
Publication Date:
August 13, 1991
Filing Date:
December 15, 1989
Export Citation:
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Assignee:
HITACHI LTD
HITACHI VLSI ENG
International Classes:
H05K7/20; H01L23/36; H01L23/373; H01L25/04; H01L25/18; (IPC1-7): H01L23/36; H01L23/373; H01L25/04; H01L25/18; H05K7/20
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)