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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH0492428
Kind Code:
A
Abstract:

PURPOSE: To reduce an irregularity in the thickness of an interlayer insulating film and to obtain a low contact resistance by a method wherein a lower-layer conductive layer and an upper-layer conductive layer are connected, on a semiconductor substrate, via a plurality of contact holes made in the interlayer insulating film and cutout parts are formed in the lower-layer conductive layer at regions between the plurality of contact holes.

CONSTITUTION: An interconnection-layer material 3 as a lower layer is applied; after that, it is patterned; the interconnection layer 3 is processed and, at the same time, cutout parts 10 are formed. Then, an interlayer insulating film 4 is formed on the surface including the parts; and an interlayer insulating film 5 is coated and formed. At this time, a coating liquid is going to flow to the direction of an arrow 9 and creeps into the cutout parts 10; and the coating liquid in proper quantities is supplied uniformly on the surface of the interconnection layer 3, and its supply condition becomes nearly uniform. Consequently, the thickness of the interlayer insulating film 5 becomes nearly equal in individual positions in which contact holes are to be formed on both sides of the cutout parts 10. Then, an interlayer insulating film 6 is deposited; after that, the contact holes 7 are formed so as to pass the film. A wiring-layer material is applied and patterned; and a wiring layer 8 is formed.


Inventors:
IMAMURA YOICHIRO
Application Number:
JP20944090A
Publication Date:
March 25, 1992
Filing Date:
August 08, 1990
Export Citation:
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Assignee:
TEXAS INSTRUMENTS JAPAN
International Classes:
H01L21/302; H01L21/3065; H01L21/3205; H01L21/768; H01L27/105; H01L29/41; (IPC1-7): H01L21/302; H01L21/3205; H01L21/90; H01L27/105; H01L29/44
Attorney, Agent or Firm:
Kiyotaka Sasaki (1 outside)



 
Next Patent: JPH0492429