Title:
半導体装置製造およびその製造方法
Document Type and Number:
Japanese Patent JP4335932
Kind Code:
B2
Abstract:
A technology that improves the reliability of a semiconductor device and realizes a high performance by a laminated structure that has enough barrier properties against copper, reduces the wire delay time by lowering the capacitance between wirings and improves the adhesion between wirings is provided. There is a semiconductor device having: a first copper wiring layer, a first barrier layer on the first copper wiring layer, a silicon oxide series porous insulating layer on the first barrier layer, a second barrier layer on the silicon oxide series porous insulating layer, and a second copper wiring layer on the second barrier layer, wherein at least one of the first barrier layer and the second barrier layer consists of an amorphous carbon film, wherein a silicon series insulating layer is directly connected between the amorphous carbon film and any of the first copper wiring layer or the second copper wiring layer.
Inventors:
Tsukasa Itani
Application Number:
JP2007046959A
Publication Date:
September 30, 2009
Filing Date:
February 27, 2007
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L21/768; H01L21/314; H01L23/522
Domestic Patent References:
| JP2007134425A | ||||
| JP2004241464A | ||||
| JP2008047817A |
Foreign References:
| WO2008078649A1 |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku
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