To inhibit discharge from a chip back face at the time of mounting a semiconductor chip, and inhibit discharge from a back face, end faces, edges and vertexes of a semiconductor against charging after completion of the mounting thereby to reduce damages of the semiconductor.
A semiconductor device manufacturing method comprises a dicing process of forming a hardened resin layer on a back face of a semiconductor chip to provide a structure protruding from a semiconductor. By bonding the semiconductor chip and wiring in this state, electrostatic discharges, which penetrate the semiconductor chip is prevented. In addition, an underfill resin wets up to the protruded part to cover a back face, end faces, edges and vertexes of the semiconductor thereby to prevent electrostatic discharges.
WO/2019/066884 | SEMICONDUCTOR PACKAGES, AND METHODS FOR FORMING SEMICONDUCTOR PACKAGES |
JP2009049955 | PIEZOELECTRIC OSCILLATOR |
WO/2019/212677 | INNOVATIVE FAN-OUT PANEL LEVEL PACKAGE (FOPLP) WARPAGE CONTROL |
ISADA NAOYA
SAKAMA ISAO
SAGAWA SHIGERU
SHIBATA DAISUKE
Yuji Toda
Shigemi Iwasaki