Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JPH07326729
Kind Code:
A
Abstract:

PURPOSE: To cut down the wiring length while making a chip smaller and the rapid operation feasible by a method wherein a plurality of devices indpendently performing electric operations on semiconductor rods provided on a substrate are formed.

CONSTITUTION: Within semiconductor rods 5, the first N layer, P layer, the second N layer, i layer, the third layer, the second P layer, the fourth layer are formed from a GaAs substrate (111) side. Next, a plurality of electrodes 3 are provided on the substrate 1 to provide insulating layers 2 between the electrodes 3. Besides, the electrodes 3 connect the semiconductor rods 5 while the electrodes 3 connected to the i layer is grounded. Furthermore, NPN transistors are respectively and electrically devided to be formed on the upper and lower parts of the semiconductor rods 5 while a protective film 4 is provided on the electrode 3 connected to the fourth N layer. Through these procedures, the wiring length can be cut down making a chip smaller and the rapid operation feasible.


Inventors:
HARAGUCHI KEIICHI
HIRUMA TAKEYUKI
KATSUYAMA TOSHIO
SHIMADA JUICHI
Application Number:
JP11781694A
Publication Date:
December 12, 1995
Filing Date:
May 31, 1994
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD
International Classes:
H01L29/06; H01L21/8222; H01L27/00; H01L27/082; H01L29/66; (IPC1-7): H01L29/66; H01L21/8222; H01L27/00; H01L27/082; H01L29/06
Domestic Patent References:
JPH0697425A1994-04-08
Attorney, Agent or Firm:
Junnosuke Nakamura