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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2012054454
Kind Code:
A
Abstract:

To provide a semiconductor device manufacturing method which can form a thick silicide layer while inhibiting occurrence of short circuits between gate electrodes and a semiconductor substrate caused by silicide layer growth.

The semiconductor manufacturing method comprises the steps of forming gate electrodes 51, 52 on a side face of a pillar 26 via a gate insulator 27, forming an upper impurity diffusion region 36 on a top edge of the pillar 26, forming a cylinder hole 71 penetrating interlayer insulators 39, 68 formed on the upper impurity diffusion region 36 and exposing a top face of the upper impurity diffusion region 36, forming a silicon film 42 at the bottom part of the cylinder hole 71 to cover the top face of the upper impurity diffusion region 36 and fill a part of the cylinder hole 71, and forming a lower electrode 57 so as to cover a top face of the silicon film 42 and an inner surface of the cylinder hole 71 above the silicon film 42 while forming a silicide layer 43 by reacting Si contained in the silicon film 42 with a metal contained in the lower electrode 57 by use of heat generated in forming the lower electrode 57.


Inventors:
MIKASA NORIAKI
Application Number:
JP2010196729A
Publication Date:
March 15, 2012
Filing Date:
September 02, 2010
Export Citation:
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Assignee:
ELPIDA MEMORY INC
International Classes:
H01L21/8242; H01L27/108
Attorney, Agent or Firm:
Sumio Tanai
Tadashi Takahashi
Naoki Ofusa
Kazunori Onami