Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2012134212
Kind Code:
A
Abstract:
To increase performance of a semiconductor device.
There are formed a gate electrode GE1 serving as a metal gate electrode for an n-channel MISFET and a dummy gate electrode GE2 for a p-channel MISFET. Subsequently formed are source/drain regions for the n-channel MISFET and source/drain regions for the p-channel MISFET, respectively. Subsequently, the dummy gate electrode GE2 is removed and a metal gate electrode for the p-channel MISFET is formed in a concavity generated due to removal of the dummy gate electrode GE2.
Inventors:
YUGAMI JIRO
Application Number:
JP2010282887A
Publication Date:
July 12, 2012
Filing Date:
December 20, 2010
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L27/092; H01L21/28; H01L21/336; H01L21/8238; H01L29/423; H01L29/49; H01L29/78
Attorney, Agent or Firm:
Yamato Tsutsui
Atsushi Sugada
Akiko Tsutsui
Toru Nakahara
Tetsuya Sakaji
Atsushi Sugada
Akiko Tsutsui
Toru Nakahara
Tetsuya Sakaji