Title:
半導体装置製造方法
Document Type and Number:
Japanese Patent JP7224138
Kind Code:
B2
Abstract:
An object of the present invention is to provide a technique suitable for achieving low wiring resistance and reducing a variation in the resistance value between semiconductor elements to be multilayered in a method of manufacturing a semiconductor device in which the semiconductor elements are multilayered through laminating semiconductor wafers via an adhesive layer. The method of the present invention includes first to third processes. In the first process, a wafer laminate Y is prepared, the wafer laminate Y having a laminated structure including a wafer 3, wafers 1T with a thickness from 1 to 20 um, and an adhesive layer 4 with a thickness from 0.5 to 4.5 μm interposed between a main surface 3a of the wafer 3 and a back surface 1b of the wafer 1T. In the second process, holes extending from the main surface 1a of the wafer 1T and reaching a wiring pattern of the wafer 3 are formed by a predetermined etching treatment. In the third process, the holes are filled with a conductive material to form through electrodes. The adhesive layer 4 has an etching rate of 1 to 2 μm/min in dry etching performed using an etching gas containing CF4, O2, and Ar at a volume ratio of 100:400:200 under predetermined conditions.
Inventors:
Naoko Tsuji
Application Number:
JP2018199014A
Publication Date:
February 17, 2023
Filing Date:
October 23, 2018
Export Citation:
Assignee:
Daicel Corporation
International Classes:
H01L21/3065; C09J171/02; C09J183/04; C09J201/00; H01L21/304; H01L21/3205; H01L21/768; H01L23/522; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2016062951A | ||||
| JP2016004799A | ||||
| JP2016004835A |
Foreign References:
| WO2017061416A1 | ||||
| WO2016204115A1 |
Attorney, Agent or Firm:
Patent Attorney Corporation G-chemical
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