PURPOSE: To output different data in parallel or serial by providing a switching circuit which is controlled by the output of a chip selection decoder within a semiconductor device for memory.

CONSTITUTION: An address signal 2 addresses to a memory part 1, and the resulted 8-bit outputs RM0WRM7 is applied to a switching circuit 5. A chip selection decoder 3 compares 4-bit code signals a0Wa3 fed from outside with the 4-bit code set previously within the decoder 3 and outputs a selection signal CS when the coincidence is obtained from the comparison. This signal CS is set to logic 0, and a switch 6 is turned on and a switch 7 is turned off. Thus the output is obtained from a shift register 8 through a serial data output terminal SDO. In case no coincidence is obtained from said comparison, the switch 6 is turned off. Then a parallel data output is obtained from terminals D0WD7 via the switch 7. Thus it is possible to obtain optionally both serial and parallel outputs.