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Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Document Type and Number:
Japanese Patent JP2012089784
Kind Code:
A
Abstract:

To improve characteristics of a semiconductor device.

The semiconductor device comprises: a silicon substrate 1 whose plane orientation is (110); and a p-channel type field effect transistor formed in a p-MIS region 1B. The p-channel type field effect transistor comprises: a gate electrode GE2 arranged with a gate insulating film 3 interposed therebetween; and a source-drain region arranged inside a trench g2 provided in the silicon substrate 1 at both sides of the gate electrode GE2, and formed of SiGe having a larger lattice constant than that of Si. The trench g2 comprises: a first inclined plane whose plane orientation is (100); and a second inclined plane whose plane orientation crossing with the first inclined plane is (100), at a sidewall part positioned on the gate electrode GE2 side. According to the structure, an angle formed by the (110) plane and the (100) plane of the substrate is 45°, and the first inclined plane is formed in a relatively acute angle, thereby a compressive strain can be applied to a channel region of the p-channel type MISFET effectively.


Inventors:
YAMAGUCHI SUNAO
Application Number:
JP2010237309A
Publication Date:
May 10, 2012
Filing Date:
October 22, 2010
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L29/78; H01L21/8238; H01L21/8244; H01L27/092; H01L27/10; H01L27/11
Domestic Patent References:
JP2009043938A2009-02-26
JP2013511159A2013-03-28
JP2008218797A2008-09-18
JP2007294780A2007-11-08
JP2009026795A2009-02-05
JP2009016866A2009-01-22
Foreign References:
US20080237634A12008-10-02
Attorney, Agent or Firm:
Yamato Tsutsui
Atsushi Sugada
Akiko Tsutsui
Toru Nakahara
Tetsuya Sakaji