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Title:
SEMICONDUCTOR DEVICE PACKAGING SUBSTRATE AND PACKAGE METHOD OF SEMICONDUCTOR DEVICE USING IT
Document Type and Number:
Japanese Patent JPH0537121
Kind Code:
A
Abstract:

PURPOSE: To provide a substrate which enables easy and reliable mount of a semiconductor device wherein an outer lead is made straight and cut short and a package structure thereof.

CONSTITUTION: A recessed part 11 is formed in a region which is relevant to a package 4 to be mounted and a wiring pattern 12 is formed on a surface corresponding to a lead 3 of the package. A lead of a semiconductor device is straightened and connected onto each wiring pattern. A first substrate 1 having a through-hole in a region relevant to a package and a wiring pattern on a surface, a second substrate having a wiring pattern on a front and a rear and a third substrate having a through-hole in a region relevant to a package and a wiring pattern on a surface are laminated one by one. Wiring patterns of the first, second and third substrates are connected each other through through-holes and a multi-layer wiring structure is constituted.


Inventors:
NOUZUMI ATSUO
Application Number:
JP943091A
Publication Date:
February 12, 1993
Filing Date:
January 30, 1991
Export Citation:
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Assignee:
MITSUI HIGH TEC
International Classes:
H01L23/50; H01L25/10; H01L25/11; H01L25/18; H05K1/18; H05K3/34; H05K3/46; (IPC1-7): H01L23/50; H01L25/10; H01L25/11; H01L25/18; H05K1/18
Domestic Patent References:
JPH0193196A1989-04-12
JPS61248497A1986-11-05
JPS6296279A1987-05-02
JPS61131495A1986-06-19
JP59104568B
JPH029475B21990-03-02
JP2125373B
Attorney, Agent or Firm:
Kimura Takahisa