To reduce poor electrical characteristics caused by static electricity during the process of manufacturing a semiconductor device.

The semiconductor is structured to have first wiring 11a which is formed on a silicon substrate 1 and has connection wiring which reaches the silicon substrate 1 in an interlayer between the first wiring 11a and the substrate 1; second wiring 11b which is formed on the same layer as the first wiring at a predetermined interval of d1 from the first wiring 11a and has not connection wiring which reaches the silicon substrate 1 in the interlayer between the second wiring 11b and the substrate 1; and dummy wiring 11c which is formed on the same layer as those wiring at a predetermined interval of d2 from the second wiring 11b. This structure enables charge the second wiring 11b bears during the manufacturing process to be dispersed to the dummy wiring 11c, thus enabling the alleviation of a potential difference between the first wiring 11a and the second wiring 11b compared with a case that the dummy wiring 11c is not provided. As a result, the electrostatic discharge damage of a second interlayer dielectric 9 in the manufacturing process can be controlled.