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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE WITH MULTILAYER INTERCONNECTION STRUCTURE
Document Type and Number:
Japanese Patent JPH04192444
Kind Code:
A
Abstract:

PURPOSE: To improve step coverage without deteriorating integration and high- speed and attain highly reliable layer-to-layer connecting structure by providing an uplifting table which uplifts bottom layer wiring at the bottom of bottom layer wiring in a connecting area which connects the bottom layer wiring and top layer wiring which are insulated by a layer insulating film.

CONSTITUTION: An uplifting table 13 is formed on a semiconductor substrate 11 through an insulating film 12, and bottom layer wiring 14 is formed on the uplifting table 13 and on an insulating film 12. Namely, the uplifting table 13 is a table which partly uplifts the bottom wiring 14, and the bottom layer wiring 14 is formed by permitting the part on the uplifting table 13 to be uplifted. A layer insulating film 15 is formed on the bottom layer wiring 14, and top layer wiring 17 connected with the bottom wiring 14 through a through hole 16 formed above the uplifting table 13 is formed by being insulated from the bottom wiring 14 by means of the layer insulating film 15. Thus, step coverage is improved and connection hindrance is suppressed without deteriorating integration and high speed, and high reliability is attained.


Inventors:
IWAI MASAAKI
Application Number:
JP32099890A
Publication Date:
July 10, 1992
Filing Date:
November 27, 1990
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/28; H01L21/768; H01L23/522; (IPC1-7): H01L21/28; H01L21/90
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)