Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2004180125
Kind Code:
A
Abstract:
To correctly and stably generate a plurality of internal clock signals with different phases and/or frequencies.
An operation control signal (Iref) for an oscillator (3) for generating an internal clock signal (CLK1) subjected to phase synchronization with the phase of a basic clock signal (BCLK) is given to a second internal clock generation circuit (10). In the second internal clock generation circuit, a control signal for adjusting a phase/frequency difference between a synchronous object signal (DATA) and a second internal clock signal is generated with the given operation control signal as a reference to adjust the phase/frequency of the second internal clock signal.
Inventors:
HARAGUCHI YOSHIYUKI
ADACHI SEI
UCHIUMI TAKASHI
KOMATSU DANICHI
KOSAKA HIROYUKI
ADACHI SEI
UCHIUMI TAKASHI
KOMATSU DANICHI
KOSAKA HIROYUKI
Application Number:
JP2002345894A
Publication Date:
June 24, 2004
Filing Date:
November 28, 2002
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
H01L21/822; G06F1/06; G06F1/08; H01L27/04; H03L7/087; H03L7/113; (IPC1-7): H03L7/087; H01L21/822; H01L27/04; H03L7/113
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
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