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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2007194486
Kind Code:
A
Abstract:

To manufacture an anti-fuse element by utilizing an already existent manufacturing process as it is, without altering an already existent manufacturing process of a MOS transistor.

In a semiconductor device, the anti-fuse element 103 has a predetermined region 11b corresponding to a channel region 11a of a cell transistor 101 and having the same conductivity type as the channel region 11a, an insulating film 12b corresponding to the gate insulating film 12a of the cell transistor 101, an electrode 13b corresponding to the gate electrode 13a of the cell transistor 101 and having the same conductivity type as the gate electrode 13a, and diffusion regions 14b, 14b' corresponding to source/drain regions 14a, 14a' of the cell transistor 101 and having the same conductivity as the source/drain regions 14a, 14a'. Hereupon, the anti-fuse element 103 is formed by utilizing the manufacturing process of the cell transistor 101 as it is.

COPYRIGHT: (C)2007,JPO&INPIT


Inventors:
SAINO KANTA
Application Number:
JP2006012716A
Publication Date:
August 02, 2007
Filing Date:
January 20, 2006
Export Citation:
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Assignee:
ELPIDA MEMORY INC
International Classes:
H01L21/82; H01L21/822; H01L21/8242; H01L27/04; H01L27/108
Domestic Patent References:
JP2000123592A2000-04-28
JPH05190801A1993-07-30
JPH11238860A1999-08-31
JPH0582641A1993-04-02
Attorney, Agent or Firm:
Takuya Yamazaki