To provide a semiconductor device with high reliability by arranging an antenna diode using layout technique for blocking an influence of PID (Plasma Induced Damage) and then preventing deterioration in characteristics of a field-effect transistor due to the PID.

A first antenna diode AD1 and a gate electrode 16 of an nMIS are electrically connected to each other through wiring M1 of a first layer, and a second antenna diode AD2 and another semiconductor element are electrically connected to each other through wiring M4 of a fourth layer (wiring one layer below top-layer wiring in an antenna block) from wiring M1 of a first layer. Further, wiring M4 of the fourth layer electrically connecting with the first antenna diode AD2 and wiring M4 of the fourth wiring electrically connecting with the second antenna diode AD2 are connected by wiring 25 of a fifth layer as the top-layer wiring in the antenna block.