To reduce the operating voltage of a semiconductor device including a nonvolatile memory.
The semiconductor device includes a nonvolatile memory NVM provided on a silicon substrate 1. Each memory cell MC1 includes an n-channel write transistor QW1 and a capacitor CM1 provided on a memory p-well PW1, and a p-channel erase transistor QE1 provided on a memory n-well NW1. The elements are formed across a memory gate insulating film MI1, and share a portion of a floating gate electrode FG1 in the floating state. The write transistor QW1 is an element that injects electrons into the floating gate electrode FG1 for writing. The capacitor CM1 is an element for controlling the potential of the floating gate electrode FG1. The erase transistor QE1 is an element that extracts electrons of the floating gate electrode FG1 for erasure.
NAKAGAWA KOICHI
KAMATA SHOGO
KIYOFUJI SHIGEMITSU
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