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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2012222122
Kind Code:
A
Abstract:

To achieve high mounting performance and high connection reliability in a semiconductor device by inhibiting warp due to a thermal expansion difference between a semiconductor element and a package substrate on which the semiconductor element is mounted.

A semiconductor device comprises: a semiconductor chip 1 connected on a substrate 4 via bumps 2; and a mold resin 3 provided around the semiconductor chip 1. By providing the mold resin 3 so as to satisfy a relationship represented as B>√2×A where A represents a distance from the semiconductor chip 1 to an edge of the mold resin 3 at from a corner of the semiconductor chip to in the vicinity of a corner of the substrate 4 and B represents a distance from the semiconductor chip 1 to an edge of the mold resin 3 in the vicinity of the center of a side of the substrate 4, warp of the semiconductor device can be easily inhibited with ensuring compact size, a thin thickness and reliability.


Inventors:
OSUMI TAKATOSHI
Application Number:
JP2011085858A
Publication Date:
November 12, 2012
Filing Date:
April 08, 2011
Export Citation:
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Assignee:
PANASONIC CORP
International Classes:
H01L23/28; H01L23/29; H01L23/31
Attorney, Agent or Firm:
Morimoto International Patent Office