Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3732637
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To access a multi-way cache at a high speed.
SOLUTION: This device is equipped with a memory array, associative cell arrays 101 and 102 which input and compare part of a virtual page number with data of associative cells and output a hit signal, decoding circuits 103 and 104 which decode the offset address signal of a logical address and select one line, and word drivers 105 and 106 which are selected by ANDing the lines selected by the decoders and a way (hit signal) selected by the associative cell arrays. Consequently, only one line is activated in one way, so word lines are never activated in the same way at the same time by mistake, so no timing margin is needed when a word line is activated after the comparison of associative cells (CAMCELL). Consequently, the access time can be made shorter than before.
Inventors:
Kenichi Nagata
Koichiro Ishibashi
Koichiro Ishibashi
Application Number:
JP35927497A
Publication Date:
January 05, 2006
Filing Date:
December 26, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F12/08; G06F12/10; G11C11/34; G11C15/00; G11C15/04; (IPC1-7): G06F12/08; G11C15/04
Domestic Patent References:
| JP11162179A | ||||
| JP10105459A | ||||
| JP1027481A | ||||
| JP9180468A | ||||
| JP87580A | ||||
| JP6131265A | ||||
| JP5282877A | ||||
| JP4262436A | ||||
| JP1149153A |
Foreign References:
| WO1996029705A1 |
Attorney, Agent or Firm:
Mitsumasa Tokuwaka
Yasuo Sakuta
Yasuo Sakuta