Title:
半導体装置
Document Type and Number:
Japanese Patent JP5197241
Kind Code:
B2
Abstract:
The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.
Inventors:
Masanao Yamaoka
Kenichi Nagata
Kenichi Nagata
Application Number:
JP2008223290A
Publication Date:
May 15, 2013
Filing Date:
September 01, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G11C11/413
Domestic Patent References:
| JP2007035171A | ||||
| JP2005085349A | ||||
| JP5504648A | ||||
| JP2007179593A |
Attorney, Agent or Firm:
Shizuyo Tamamura