Title:
Semiconductor device
Document Type and Number:
Japanese Patent JP6080544
Kind Code:
B2
Abstract:
An increase in chip area and a deterioration of delay performance are reduced without dummy cells or dummy gates for plasma damage, suppressing an increase in the capacitance of dummy cells or dummy gates and a deterioration of wiring. In the case where bit wires or bit contacts used for the DRAM cell region of a circuit block are used as wires and contacts for a logic circuit region, gate electrodes affected by plasma damage are automatically analyzed after the completion of placement and routing. The well contact region (well potential diffusion layer) of the logic circuit region contains dummy contacts for plasma damage.
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Inventors:
Masaru Sato
Application Number:
JP2012283696A
Publication Date:
February 15, 2017
Filing Date:
December 26, 2012
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/8242; H01L21/3205; H01L21/768; H01L21/8234; H01L23/522; H01L27/088; H01L27/108
Domestic Patent References:
| JP2005259842A | ||||
| JP2006344773A | ||||
| JP2000183043A | ||||
| JP2001110810A | ||||
| JP7321118A | ||||
| JP2006186315A | ||||
| JP2003031677A | ||||
| JP2011066126A |
Attorney, Agent or Firm:
Minoru Kudo
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