Title:
Semiconductor device
Document Type and Number:
Japanese Patent JP6126344
Kind Code:
B2
Abstract:
A metal oxide layer is in contact with an interlayer insulating layer covering a transistor, and has a stacked-layer structure including a first metal oxide layer having an amorphous structure and a second metal oxide layer having a polycrystalline structure. In the first metal oxide layer, there are no crystal grain boundaries, and grid intervals are wide as compared to those in a metal oxide layer in a crystalline state; thus, the first metal oxide layer easily traps moisture between the lattices. In the second metal oxide layer having a polycrystalline structure, crystal parts other than crystal grain boundary portions have dense structures and extremely low moisture permeability. Thus, the structure in which the metal oxide layer including the first metal oxide layer and the second metal oxide layer is in contact with the interlayer insulating layer can effectively prevent moisture permeation into the transistor.
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Inventors:
Masahiro Watanabe
Masuo Masuyama
Takuya Handa
Kenichi Okazaki
Masuo Masuyama
Takuya Handa
Kenichi Okazaki
Application Number:
JP2012210014A
Publication Date:
May 10, 2017
Filing Date:
September 24, 2012
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L29/786; H01L21/316; H01L21/336
Domestic Patent References:
| JP2010186860A | ||||
| JP2011142309A | ||||
| JP2158172A | ||||
| JP5167074A | ||||
| JP6125087A | ||||
| JP2011077509A | ||||
| JP2010166030A | ||||
| JP2006156961A |