Title:
半導体装置
Document Type and Number:
Japanese Patent JP7027506
Kind Code:
B2
Abstract:
A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.
Inventors:
Kiyoshi Kato
Shuhei Nagatsuka
Hiroki Inoue
Takanori Matsuzaki
Shuhei Nagatsuka
Hiroki Inoue
Takanori Matsuzaki
Application Number:
JP2020185328A
Publication Date:
March 01, 2022
Filing Date:
November 05, 2020
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L29/786; H01L21/336; H01L21/8242; H01L27/108; H01L27/1156; H01L29/788; H01L29/792
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