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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH02105563
Kind Code:
A
Abstract:

PURPOSE: To improve the dielectric breakdown strength and reliability of a gate oxide film by forming the emitter electrode of a bipolar transistor as well as a gate electrode of a MOS-FET by the use of a polycrystalline silicon layer containing different impurities.

CONSTITUTION: An npn-type bipolar transistor and an n-channel type MOS-FET are disposed respectively in n-type and p-type wells 4 and 5 which are formed on an n-type epitaxial growth silicon layer located on a p-type Si substrate 1. The emitter electrode 13 of the bipolar transistor consists of an n+ type polycrystal silicon layer containing As and the gate electrode 8 of a MOS-FET consists on an n+ type polycrystalline silicon layer containing phosphorus (p) and they are made up by the polycrystalline silicon layers which are formed by forming different layers. In this way, the doping method and the amount of doping with respect to impurities to be doped into polycrystalline silicon layers are established independently with each element and impurity-doping to the gate electrode is thus optimized. Such optimum impurity-doping improves exceedingly dielectric breakdown strength of the gate oxide film and makes its reliability high.


Inventors:
FURUHATA TOMOYUKI
Application Number:
JP25883688A
Publication Date:
April 18, 1990
Filing Date:
October 14, 1988
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H01L29/73; H01L21/331; H01L21/8222; H01L21/8248; H01L21/8249; H01L27/06; H01L29/732; (IPC1-7): H01L21/331; H01L27/06; H01L29/73
Attorney, Agent or Firm:
Masanori Ueyanagi (1 outside)



 
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