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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH04364743
Kind Code:
A
Abstract:

PURPOSE: To realize a high connection reliability of a semiconductor device with a decrease in resin-induced residual stress by recessing and grooving a board.

CONSTITUTION: A board 6 with wiring patterns 7 is etched for grooves 10 and recesses 11. Next, the board 6 is coated with an epoxy resin 8 containing conductive particles 9, and bump electrodes 5 on a semiconductor chip 1 are positioned to the wiring patterns 7 on the board 6; then, while the semiconductor chip 1 is pressurized to vary conductive particles 9 between a bump electrode 5 and a wiring pattern 7, the semiconductor chip 1 is heated to harden the resin 8. At this time, an extra amount of resin 8 is exhausted through the groove 10. This process can reduce loads on the semiconductor chip, prevent its breakdown, and further improve connection reliability between the semiconductor chip and the board.


Inventors:
YAMAZAKI YASUO
Application Number:
JP13932991A
Publication Date:
December 17, 1992
Filing Date:
June 12, 1991
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H01L21/60; H05K1/18; H05K3/32; (IPC1-7): H01L21/60; H05K1/18
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)



 
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