Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0669234
Kind Code:
A
Abstract:
PURPOSE: To provide a method of manufacturing a polysilicon TFT, without the use of an ion-implantation process and without producing parasitic capacitance. CONSTITUTION: A first polysilicon layer 11 is first formed on a substrate, and then a dielectric layer 12 is formed on a part of the first layer. A second polysilicon layer 13 is formed on the dielectric layer with the same area as that of the dielectric layer. A layer 14, comprising a refectory metal such as titanium is deposited on the second polysilicon layer 13 and on an exposed region of the first polysilicon layer 11. The metallic layer and the polysilicon layer are brought into reaction with annealing, for example, to form a silicate region and further form source, gate, and drain electrodes 15, 16, and 17. Then a non-reacting portion of the metal layer is removed with a selective etching.
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Inventors:
PINERAPI AN KOKUSUN
Application Number:
JP10178891A
Publication Date:
March 11, 1994
Filing Date:
April 08, 1991
Export Citation:
Assignee:
GEN ELECTRIC CO PLC
International Classes:
H01L29/40; H01L21/3213; H01L21/336; H01L29/45; H01L29/49; H01L29/78; H01L29/786; (IPC1-7): H01L21/336; H01L21/324; H01L29/40; H01L29/784
Attorney, Agent or Firm:
Nobuyuki Iida
Next Patent: 光ファイバ母材の焼結炉