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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH09166646
Kind Code:
A
Abstract:

To provide a self-test circuit technology in which a circuit to be tested is tested fro dynamic failure through a relatively simple constitution and a propagation delay time is made constant.

A test signal is applied from an input signal generation circuit 1 to a circuit 3 to be tested and a test results output signal is latched by a latch circuit 8 in response to a strobe input signal (strobe signal). The strobe signal has period T identical to that of a clock signal being fed to a sync clock input signal terminal and controls the phase difference tθ. Consequently, the strobe position is varied and an output signal sequence from the latch circuit 8 is compressed by an output signal compression circuit 5 in synchronism with a clock signal. Subsequently, the compressed signal is compared by a comparator 7 with an expected value signal from an output signal expected value generation circuit 6 and it is judged whether the circuit 3 to be tested is dynamically good or bed through a judged value output signal terminal.


Inventors:
OGAWA TADAHIKO
Application Number:
JP34770895A
Publication Date:
June 24, 1997
Filing Date:
December 15, 1995
Export Citation:
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Assignee:
NEC CORP
International Classes:
G01R31/3185; G06F11/22; G01R31/28; (IPC1-7): G01R31/28; G06F11/22
Attorney, Agent or Firm:
Asato Kato