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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH09289305
Kind Code:
A
Abstract:

To relax the field concentration on the ends of field plate electrodes, without comparatively increasing the thickness of an insulation layer by partly burying insulator plates between a first and second insulation layers beneath the ends of the field plate electrodes.

Non-doped polycrystalline Si-made insulator plates 8 are buried between a first and second insulation layers 5, 6 so as to raise the ends of field plate electrodes 7. This allows the thicknesses d1, d2 of the insulation layers between the field plate electrodes 7 and semiconductor substrate 1 to be increased away from p-n junctions 3 to outside diffused regions 2. If hence a depletion layer 10 is formed around the p-n junctions 3 to result in generation of an electric field, the field concentration at the ends of the field plate electrodes 7 can be relaxed to improve the breakdown field intensities at the p-n junctions 3 and the insulation layer beneath the ends of the field plate electrodes 7.


Inventors:
IMOTO SHINYA
Application Number:
JP9847496A
Publication Date:
November 04, 1997
Filing Date:
April 19, 1996
Export Citation:
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Assignee:
ROHM CO LTD
International Classes:
H01L29/41; H01L21/76; H01L29/06; H01L29/78; (IPC1-7): H01L29/41; H01L21/76; H01L29/78