PURPOSE: To enable high speed operation of a semiconductor device by surrounding the drain region of an electrostatic induction transistor by thick insulating film and channel region to thereby reduce the drain resistance and capacitance so as to improve its gm (mutual conductance).

CONSTITUTION: N- type semiconductor region 3 is formed on an N+ type semiconductor substrate 1, and with P+ type regions 5, 6 and N+ type region 7 exposed on the main surfaces therein. The region 7 is entirely surrounded by an insulating film 28 and a channel forming portion 35 in a manner that P+ type resion 25 making contact with the region 5 is so buried in the region 3 to face oppositely to the film 28. Thus, a PNP transistor Tr having an emitter of the region 6, a base of the region 3 and collector of regions 5, 25 is formed with such electrostatic induction type semiconductor logic device in a manner that the region 1 operates as a source, the regions 5, 25 as a gate and the portion 35 in the region 3 as a channel with the region 7 as a drain as an electrostatic induction type transistor SIT which is controlled via the gate regions 5, 25 for opening or closing the current passage of the channel portion 35.