PURPOSE: To reduce the leakage current of cells by a method wherein a deep region of a substrate is provided with an impurity region of the same conductivity type as that of the substrate and of higher concentration.
CONSTITUTION: A P+ region 2 is formed after a thermal oxide film 11 is formed on the (100) plane of the P type Si substrate 1. Next, a P type Si12 is epitaxially grown after removal of the thermal oxide film 11. Then, a field oxide film 13 is formed to create an element isolating region, and thereafter a nitride film 14 and a phospho-silicate glass 15 are deposited. The glass 15, the nitride film 14, and an oxide film 16 are removed by the photoetching method in the part to serve as a capacitor, and the epitaxial layer 12 and the Si substrate 1 are dug down by using the film 15 as a mask. After removal of the films 15, 14, and 16, a three-layer film made of an oxide film 17, a nitride film 18, and an oxide film 19 are formed. Further, a gate electrode 20, a gate oxide film 22, a gate electrode 21, and source-drain N+ impurity regions 23 are formed, resulting in the completion of a memory cell. This manner enables the fine formation of the memory element and the increase in refresh time.
| JP6203154 | Organic molecule memory |
| WO/2005/101539 | LAYERED RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF FABRICATION |
| JPS5627450 | SEMICONDUCTOR RANDOM NUMBER GENERATOR |
NISHIMURA REIKO
YAMAGUCHI KEN
HAGIWARA TAKAAKI
SUNAMI HIDEO
