PURPOSE: To enhance the reliability of a semiconductor device by arranging a power source voltage wiring layer in the intermediate between upper and lower signal wiring layers to hardly introduce a noise to other signal wirings, thereby preventing an erroneous operation.
CONSTITUTION: Upper and lower signal wiring layers 2, 3 are arranged through a power source voltage wiring layer 1 in the intermediate therebetween as a wiring layer and hence a shielding wiring layer applied with certain fixed potential. One end of a connector wire 6 is bonded to the electrode pads (not shown) of a semiconductor chip 4 mounted on a mounting substrate 5, the other end of the wire 6 is bonded to the wiring layer 2 on the upper layer, the upper layer signal wire 2 is (though not shown) connected with the lower layer signal wire 3 via a through hole, thereby externally leading a signal in a semiconductor chip 4 from the external terminal 7 provided at the lower portion of the substrate 5. According to an embodiment, a signal is inputted to the wire 2 as shown in an equivalent circuit, and even if the signal is fluctuated, a noise is not introduced to the wire 3 by the shielding effect of the layer 1.
HOSOSAKA HIROSHI
KOIKE JIYUNICHI
ITOU TSUNEO
