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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS62122256
Kind Code:
A
Abstract:

PURPOSE: To enhance the integration density of a semiconductor device, by providing electric conduction between mother chips through wires, which are connected to the pads of the mother chips.

CONSTITUTION: Wiring layer 5 are formed in order to provide conduction between mother chips 4 or to the outside on a wiring substrate 2. A part of the wiring layer is electrically connected to a lead pin 11, which is provided at the side part of the wiring substrate 2. Wiring layers 12 are formed on the chips 4 by a means such as aluminum evaporation. The circuit forming surface of semiconductor pellet 3 is attached to each chip 4 through a copper bump electrode 7. One end of a piece of wire 8 is heated and fused, and a ball is formed and compressed to a bonding pad 6. Thus connection to the wire 8 is performed. The other end of the wire 8 is moved on the other pad 6. The side part of the wire 8 is compressed, and the wire is connected. Electric conduction between the chips 4 and to the outside is achieved by wires 8a hooked on the pads 7 of the chip 4 and the wiring layers 5 on the substrate 2. The surface of the substrate is covered with a cap 10 through low-melting-point glass and the like, and airtight sealing is achieved.


Inventors:
UDA TAKAYUKI
TAKEO YOSHIHISA
Application Number:
JP26111685A
Publication Date:
June 03, 1987
Filing Date:
November 22, 1985
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L23/52; H01L23/14; H01L25/065; (IPC1-7): H01L23/52
Attorney, Agent or Firm:
Katsuo Ogawa



 
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