Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS62291215
Kind Code:
A
Abstract:
PURPOSE: To obtain a semiconductor having a simple timing pulse generating circuit by providing a reference delaying circuit group to generate plural pulses in which a rise and a fall are not overlapped from a single input pulse and obtaining the logic of the output signal of the reference delaying circuit group.
CONSTITUTION: An input pulse 0 is delayed by respective delaying circuits delaying circuits 4 of a delaying circuit part and comes to be signals D1∼D4. Since any of the rise and fall time points of these signals D1∼D4 is different, these signals D1∼D4 are assembled, an assembling logic is obtained by a logic circuit part, and the rise time and the fall time can be set independently and in a wide time range.
Inventors:
IKENAGA SHINICHI
HORIGUCHI SHINJI
AOKI MASAKAZU
NAKAGOME YOSHINOBU
SHIMOHIGASHI KATSUHIRO
HORIGUCHI SHINJI
AOKI MASAKAZU
NAKAGOME YOSHINOBU
SHIMOHIGASHI KATSUHIRO
Application Number:
JP13365386A
Publication Date:
December 18, 1987
Filing Date:
June 11, 1986
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H03K5/15; G06F1/06; G11C11/34; G11C11/407; G11C11/4076; H03K5/04; H03K5/13; (IPC1-7): G11C11/34; H03K5/04; H03K5/13; H03K5/15
Attorney, Agent or Firm:
Katsuo Ogawa