Title:
半導体装置及び半導体装置の駆動回路
Document Type and Number:
Japanese Patent JP4437655
Kind Code:
B2
Abstract:
A PMOS transistor (Q 2 ) provided for developing a short circuit between the base and emitter of an N-type IGBT during turn-OFF includes a P diffusion region ( 5 ), a P diffusion region ( 6 ), and a conductive film ( 10 ) and a second gate electrode ( 15 ) provided via a gate oxide film ( 21 ) on a surface of an N- epitaxial layer ( 2 ) between the P diffusion regions ( 5 and 6 ). The gate oxide film ( 21 ) is formed in a thickness having a gate breakdown voltage higher than the element breakdown voltage of a typical field oxide film and the like.
Inventors:
Tomohide Terashima
Application Number:
JP2003344314A
Publication Date:
March 24, 2010
Filing Date:
October 02, 2003
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L21/8249; H01L21/8238; H01L29/70; H01L27/06; H01L27/092; H01L29/73; H01L29/739; H03K17/04
Domestic Patent References:
| JP11135794A | ||||
| JP6132525A | ||||
| JP6169062A | ||||
| JP7086587A | ||||
| JP11354657A | ||||
| JP62154666A | ||||
| JP2003243548A |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita