Title:
Semiconductor devices and semiconductor device design methods
Document Type and Number:
Japanese Patent JP6328974
Kind Code:
B2
Abstract:
A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.
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Inventors:
Tatsuki Mogi
Application Number:
JP2014069125A
Publication Date:
May 23, 2018
Filing Date:
March 28, 2014
Export Citation:
Assignee:
Mega Chips Co., Ltd.
International Classes:
H01L21/82; G06F17/50; H01L21/3205; H01L21/768; H01L21/822; H01L23/522; H01L27/04
Domestic Patent References:
JP63152144A | ||||
JP2000082743A | ||||
JP3104258A | ||||
JP2007173760A | ||||
JP2004103821A | ||||
JP2003124334A | ||||
JP2008187010A |
Attorney, Agent or Firm:
Gwangyang International Patent Office
Hideaki Shioya
Hideaki Shioya
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