Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP5016884
Kind Code:
B2
Abstract:
A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.
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Inventors:
Hiroyuki Enomoto
Taro Asai
Shuntaro Machida
Taro Asai
Shuntaro Machida
Application Number:
JP2006266282A
Publication Date:
September 05, 2012
Filing Date:
September 29, 2006
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L29/84; H01L21/306; H04R19/00; H04R19/04; H04R31/00
Domestic Patent References:
| JP3002523A | ||||
| JP2001298012A | ||||
| JP2006211185A |
Attorney, Agent or Firm:
Yamato Tsutsui