Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP6731522
Kind Code:
B2
Abstract:
Provided are a semiconductor device which can shorten reverse recovery time without increasing leakage current between the drain and the source, and a fabrication method for such semiconductor device. The semiconductor device includes: a first base layer (12); a drain layer (10) disposed on the back side surface of the first base layer (12); a second base layer (16) formed on the surface of the first base layer (12); a source layer (18) formed on the surface of the second base layer (16); a gate insulating film (20) disposed on the surface of both the source layer (18) and the second base layer (16); a gate electrode (22) disposed on the gate insulating film (20); a column layer (14) formed in the first base layer (12) of the lower part of both the second base layer (16) and the source layer (18) by opposing the drain layer (10); a drain electrode (28) disposed in the drain layer (10) ; and a source electrode (26) disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer (14) to form a trap level locally.
Inventors:
Toshio Nakajima
Application Number:
JP2019108642A
Publication Date:
July 29, 2020
Filing Date:
June 11, 2019
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H01L21/336; H01L29/06; H01L29/78
Domestic Patent References:
| JP2003101022A | ||||
| JP2007150142A | ||||
| JP9121052A | ||||
| JP8227895A |
Attorney, Agent or Firm:
Hidekazu Miyoshi
Keishin Terayama
Keishin Terayama