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Title:
半導体装置およびそのテスト方法
Document Type and Number:
Japanese Patent JP5629309
Kind Code:
B2
Abstract:
It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

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Inventors:
伊藤 潔人
津野田 賢伸
佐圓 真
Application Number:
JP2012505339A
Publication Date:
November 19, 2014
Filing Date:
March 15, 2010
Export Citation:
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Assignee:
株式会社日立製作所
International Classes:
G01R31/28; G06F11/22; H01L21/822; H01L27/04
Domestic Patent References:
JP2000227457A2000-08-15
JP2001141790A2001-05-25
JPH11174122A1999-07-02
Attorney, Agent or Firm:
Tsutsui Daiwa



 
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