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Title:
SEMICONDUCTOR ELEMENT MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2013197264
Kind Code:
A
Abstract:

To provide a semiconductor element manufacturing method which enables uniform bonding or a semiconductor wafer and a support substrate at a low temperature with less voids in junction of a semiconductor layer and a thermally-conductive support substrate in manufacturing of a semiconductor element such as an LED element which uses the thermally-conductive support substrate, and which prevents warpage or breakage of the semiconductor wafer and the support substrate caused by junction processing and subsequent removal of a growth substrate, thereby achieving excellent productivity, yield and reliability.

A semiconductor element manufacturing method comprises: a step of forming on a first substrate 11, an element structure layer 13 including semiconductor layers; a step of forming a first junction layer 15 on the element structure; a step of forming a second junction layer 23 on a second substrate 21; and a step of thermocompression bonding the first junction layer and the second junction layer in an opposed manner. One of the first junction layer and the second junction layer is a layer composed of Au and the other is a layer composed of AuSn. The layer composed of AuSn includes a surface layer in which a content of Sn is within a range of not less than 85 wt% and not more than 95 wt%.


Inventors:
CHINONE TAKAKO
MIYAJI MAMORU
SAITO TATSUMA
AKAGI TAKANOBU
Application Number:
JP2012061935A
Publication Date:
September 30, 2013
Filing Date:
March 19, 2012
Export Citation:
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Assignee:
STANLEY ELECTRIC CO LTD
International Classes:
H01L33/02
Domestic Patent References:
JP2002373960A2002-12-26
JP2011138839A2011-07-14
JP2003200289A2003-07-15
Foreign References:
WO2005020315A12005-03-03
US20120007117A12012-01-12
Attorney, Agent or Firm:
Fujimura Joint Patent Office