Title:
半導体装置及び通信システム
Document Type and Number:
Japanese Patent JP7320927
Kind Code:
B2
Abstract:
According to one embodiment, the semiconductor device has a the transmission processing circuit 10 that converts the binary representation of binary Transmitted data Dbin_TX to a ternary transmitted data Dter_TX represented as a ternary number and generates a transmitted signal corresponding to this ternary Transmitted data Dter_TX, wherein the transmission processing circuit 10 verifies the frequency of occurrence of the values included in the ternary transmitted data Dter_TX, assigns the signal change pattern with the highest state transition to the transmitted signal logical level corresponding to the lowest occurrence value, and generates a transmitted signal.
Inventors:
Motoo Akasaka
Satoshi Kaneko
Naoki Aono
Hiroshi Watanabe
Takayuki Kokawa
Satoshi Kaneko
Naoki Aono
Hiroshi Watanabe
Takayuki Kokawa
Application Number:
JP2018125926A
Publication Date:
August 04, 2023
Filing Date:
July 02, 2018
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H03M7/06; H03M5/14
Domestic Patent References:
| JP2016539533A | ||||
| JP2015220576A | ||||
| JP2000115261A | ||||
| JP7202709A | ||||
| JP2004172971A |
Foreign References:
| US4357634 |
Other References:
MIPI Alliance,Inc.,Specification for I3C Improved Inter Integrated Circuit Version 1.0,2016年12月23日
Attorney, Agent or Firm:
Ken Ieiri