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Title:
SEMICONDUCTOR INSPECTING METHOD AND INSPECTING EQUIPMENT USING THE SAME
Document Type and Number:
Japanese Patent JPH0360140
Kind Code:
A
Abstract:

PURPOSE: To surely enable the execution of defect marking without adding marking means, by individually moving a wafer mounting stand in accordance with the size of a semiconductor element only when a semiconductor element judged as an imperfect element is present among elements subjected to simultaneous inspection, and executing marking with a marking means installed along the relative moving direction.

CONSTITUTION: Simultaneous inspection for four semiconductor elements 1 is executed by using four probe heads 5. When no imperfect elements exist in one block subjected to the simultaneous inspection, a wafer mounting stand 3 is moved in accordance with the four chip sizes. Only when an imperfect element is present, the wafer mounting stand 3 is moved in accordance with one chip size. By arranging each inner 6 with respect to the moving direction of the wafer mounting stand 3, marking is enabled for all elements. As a result, the number of inkers can be reduced to a minimum, and the increase of equipment dimension can be restrained even in the case where the number of elements for simultaneous inspection is increased.


Inventors:
SASAKI HIDETOSHI
Application Number:
JP19598589A
Publication Date:
March 15, 1991
Filing Date:
July 28, 1989
Export Citation:
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Assignee:
TOKYO ELECTRON LTD
TEL TOHOKU KK
International Classes:
H01L21/66; (IPC1-7): H01L21/66
Domestic Patent References:
JP60118237B
JPS5957443A1984-04-03
JPS54162475A1979-12-24
Attorney, Agent or Firm:
Saichi Suyama (1 person outside)



 
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