Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, CIRCUIT DESIGN SYSTEM AND CONTROL PROGRAM
Document Type and Number:
Japanese Patent JP2021015537
Kind Code:
A
Abstract:
To provide a semiconductor integrated circuit design method, a circuit design system, and a control program that can suppress backtracking of process in design process.SOLUTION: Pseudo cell information that reflects difficulty of pin access is created (S100), in timing optimization (S200), cells with relatively low difficulty of pin access are preferentially used referring to the pseudo cell information.SELECTED DRAWING: Figure 1
Inventors:
FUJIWARA SHINTARO
Application Number:
JP2019130913A
Publication Date:
February 12, 2021
Filing Date:
July 16, 2019
Export Citation:
Assignee:
KIOXIA CORP
International Classes:
G06F30/39; H01L21/82
Attorney, Agent or Firm:
Hidekazu Miyoshi
Shunichi Takahashi
Masakazu Ito
Toshio Takamatsu
Shunichi Takahashi
Masakazu Ito
Toshio Takamatsu