To perform easily detail analysis of a fault by generating a comparison signal for performing comparison operation between read out data and an expected value and outputting it to plural scan flip-flops, only when a memory cell specified by an address signal is in a range of a cell group specified based on a control signal.

Four scan flip-flops SFF 0-3 are connected in series, and a scan path for test of a RAM 1 is constituted. A comparison control circuit 6 selects a memory cell group consisting of a memory cell of at least one or more in the RAM 1 based on control signals CA<4:0>, DC<4:0>, CMP or the like supplied from a self controller or the like, generates a comparison control signal CCMP performing control for executing comparison between an expected value and data only when the memory cell selected by an address signal is indicated, and supplies it to the scan flip-flops SFF 0-3.