To obtain a semiconductor integrated circuit device which can improve the data readout speed without increasing the operation frequencies of individual internal circuits.

An SRAM array 120 is provided with a 1st column decoder 390 and a 2nd column decoder 391. A 1st column address buffer 392 and a 2nd column address buffer 393 generate a 1st SRAM column address signal iASC-1 and a 2nd column address signal iASC-2 according to an SRAM column address signal iASC and supply them to a 1st and a 2nd column decoder, which operate by turns. Each data buffer 394 of the SRAM array 120 is provided with a 1st switch circuit 397-1 and a 2nd switch circuit 397-2 and electrified under the control of respective column decoders. Consequently, the 1st and 2nd column decoders designate addresses alternately to the SRAM array 120 and data are read out by turns.