To provide a semiconductor integrated circuit device which can easily respond to the change in the memory capacity of a memory device and by which signals/data can be transmitted at a high speed and with a low electric power consumption regardless of the change in the bus wiring length.
A semiconductor chip (CH) is divided into a first semiconductor region (2) surrounded by pads (1) and a region outside the pads (1). A memory (20) is placed in the region outside the pads (1). A memory (37) placed in the first semiconductor region (2) and the memory (20) placed outside the pads (1) are coupled to a bass interface unit (33) through respectively different memory busses (36 and 39) and a selector (100). The selector (100) is driven by two-phase clock signals (P1 and P2) of the same phase.
WATANABE KATSUKICHI
IKEMOTO MASAHIKO
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