Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2004039135
Kind Code:
A
Abstract:
To generate an internal timing control signal varied at high speed without allowing the pulse width of a pulse signal to be restricted by an internal wiring load.
A plurality of main control signal generating circuits including respectively a plurality of main control signals are provided, these circuits are activated successively, and the prescribed main control signal generating circuit is reset at the time of activation of the main control signal. A local control signal is generated by utilizing the rise edge of main control signals of one side group of these plurality of groups main control signals and a fall edge of main control signals of the other groups.
Inventors:
DOSAKA KATSUMI
Application Number:
JP2002196094A
Publication Date:
February 05, 2004
Filing Date:
July 04, 2002
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
H03K19/096; G11C7/10; G11C11/407; G11C11/4076; G11C11/408; G11C11/4097; (IPC1-7): G11C11/407; G11C11/408; H03K19/096
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai