Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2993413
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To freely connect/cut off power supply to one circuit connected by a bi-directional data bus without causing a latch-up in CMOSIC having the power lines of two systems.
SOLUTION: A separation circuit 11 detecting the drop of voltage in the second power source line 6 and interrupting the transfer of a signal between an A/D converter 4 and the bi-directional data bus 7 is provided between the A/D converter 4 and the bi-directional data bus 7. When an external switch 10 cuts the second power source line 6 and power supply to the A/D converter 4 is stopped in a period when the A/D converter 4 is not used for reducing consumption current, the separation circuit detects the drop of voltage in the second power source line and separates the output data bus 9 of the A/D converter 4 from the bi-directional data bus 7.
Inventors:
IKEGAMI MASAKAZU
Application Number:
JP31123295A
Publication Date:
December 20, 1999
Filing Date:
November 29, 1995
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06F1/26; G06F3/00; H01L21/8238; H01L27/092; H03K19/00; H03K19/003; H03M1/12; (IPC1-7): G06F3/00; G06F1/26; H01L21/8238; H01L27/092; H03K19/00; H03K19/003
Domestic Patent References:
| JP7249973A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)