Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3137749
Kind Code:
B2
Abstract:
PURPOSE: To make it possible to reduce propagation to the input side of noises generated at the operation of an output circuit by supplying power source voltage and the earth electric potential of a circuit through outer terminals consisting of LOC lead frames which are separated individually.
CONSTITUTION: Power source supply wires 2, 3 for an input circuit are connected to power source supply wires 12, 13 of an inside circuit, and to bus bar lead wires 18, 19, which are connected to power source wires 14, 15, through resistor 1 and bonding wire 11 respectively. Owing to the insertion of such a resistance element, noises generated in the output circuit can be suppressed to invade on the side of the input circuit, while restraining, in direct current, ununiformity of the electric potential at power source pins. As a result, operation margin in the input circuit can be obtained, while performing simultaneous output of multiple pits to meet the demand for a larger scale circuit.
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Inventors:
Yutaka Ito
Toshiyuki Sakuta
Takumi Nasu
Toshiyuki Sakuta
Takumi Nasu
Application Number:
JP19660492A
Publication Date:
February 26, 2001
Filing Date:
June 30, 1992
Export Citation:
Assignee:
株式会社日立製作所
日本テキサス・インスツルメンツ株式会社
日本テキサス・インスツルメンツ株式会社
International Classes:
H01L23/495; H01L23/12; H01L23/50; H01L23/64; (IPC1-7): H01L23/50
Domestic Patent References:
| JP4174551A |
Attorney, Agent or Firm:
Mitsumasa Tokuwaka