SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Document Type and Number:

Japanese Patent JP3260673

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To suppress variation in delay time due to element variance resulting from a manufacture process without requiring an external control circuit for delay compensation.
SOLUTION: This device is equipped with a delay control circuit 7 which controls the delay time T1 of an output signal according to reference voltages VR1 and VR2, a delay control circuit 8 which controls the delay time T2 of the output signal OB according to the reference voltages VR1 and VR2, and a reference voltage generating circuit 6 which detects variation in threshold value among transistors constituting a logic circuit due to manufacture variance as characteristic variance originating from the manufacture process of the transistors and generates the corresponding reference voltages VR1 and VR2.

Inventors:

Masaru Hashinaga

Application Number:

JP25223597A

Publication Date:

February 25, 2002

Filing Date:

September 17, 1997

Export Citation:

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Assignee:

Kyushu NEC Corporation

International Classes:

H03K5/151; (IPC1-7): H03K5/151

Attorney, Agent or Firm:

Naoki Kyomoto (2 outside)

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